Generally, a semiconductor package is made by bonding wires from signal input/output terminals in a lead frame to corresponding input/output pads on a semiconductor chip, and molding the semiconductor chip and lead frame within package means. Accordingly, single devices and integrated circuits on a semiconductor substrate may be protected from environmental factors such as dust, moisture, electrical and mechanical loads, and the performance of the semiconductor chip may be optimized or maximized.
When semiconductor devices are packaged in such a manner, input selector mode pads are selectively bonded or not bonded (connected) to a ground voltage so that a mode is set during packaging. Since input pads receive signals at external voltage levels, buffers may be necessary to convert the external signal levels to logic signals at the chip's internal voltage levels. In a case where there is a plurality of selectable structures, selectable parameters are input through two or more pads. These parameters are decoded, thereby selecting one out of the plurality of structures, by a bonding option circuit.
FIG. 1 is a block diagram illustrating a connection structure between conventional pads and a bonding option circuit. One out of the 3.3 V mode selection pad 10, 2.5 V mode selection pad 12, and 1.8 V mode selection pad 14 is connected (bonded) to a lead frame and the others are not connected to the lead frame.
The bonding option circuit 16 is connected to the 3.3 V mode selection pad 10 and the 1.8 V mode selection pad 14. In this case, when the 3.3 V mode selection pad 10 is connected to the lead frame, the 3.3V mode selection pad 10 receives a logic high signal and the 1.8 V mode selection pad 14 receives no input signal. When the 1.8 V mode selection pad 14 is connected to the lead frame, the 1.8 V mode selection pad 14 receives a logic high signal and the 3.3 V mode selection pad 10 receives no input signal. When the 2.5 V mode selection pad 12 is connected to the lead frame, the bonding option circuit 16 does not receive a logic high signal because it is not connected to pad 12. At this time, the 3.3V mode selection pad 10 and the 1.8 V mode selection pad 14 receive no input signal. Accordingly, the bonding option circuit 16 allows the internal circuit 18 to operate with a selected internal voltage mode output of the 3.3 V mode, 2.5 V mode and 1.8 V mode, according to a signal input to a bonding pad out of the 3.3V mode selection pad 10, the 2.5 V mode selection pad 12, and the 1.8V mode selection pad 14.
FIG. 2 is a circuit diagram of a conventional bonding option circuit.
In a case where the 3.3 V mode selection pad 10 (FIG. 1) is bonded to the lead frame, the 3.3 V mode selection signal is a high signal and the 1.8 V mode selection signal is pulled low by NMOS transistors 30, 32. The 3.3 V mode selection signal is inverted through inverters 24, 26, 28 and output as a low signal, which is input to an input terminal of NAND gate 40. The 1.8 V mode selection signal is inverted through inverters 34, 36, 38 and output as a high signal, which is input to the other input terminal of NAND gate 40. NAND gate 40 NANDs the low and high signals that are input respectively to its two input terminals, thereby generating a high output signal. The high signal output from NAND gate 40 is inverted through inverter 42 to output a low signal. The low signal output from inverter 42 is input to a 2.5 V mode selection terminal of the internal circuit 18. The low signal output from inverter 28 and the low signal output from inverter 42 are input to NOR gate 44. NOR gate 44 NORs its two input signals and outputs a high signal, which is input to a 3.3 V mode selection terminal of the internal circuit 18.
In addition, the high signal output from inverter 38 and the low signal output from inverter 42 are input to NOR gate 46. NOR gate 46 NORs the two input signals and outputs a low signal to a 1.8 V selection terminal. Accordingly, the internal circuit 18 has a high signal input to the 3.3V mode selection terminal, and operates in a 3.3 V mode.
In a case where the 1.8 V mode selection pad 14 (FIG. 1) is bonded to the lead frame 11, the 1.8 V mode selection signal is a high signal and the 3.3 V mode selection signal is pulled low by NMOS transistors 20, 22. The 3.3 V mode selection signal is inverted through inverters 24, 26, 28 and output as a high signal, which is input to an input terminal of NAND gate 40. The 1.8 V mode selection signal is inverted inverted through inverters 34, 36, 38 and output as a low signal, which is input to the other input terminal of NAND gate 40. NAND gate 40 NANDs the high and low signals that are input respectively to its two input terminals, thereby generating a high output signal. The high signal output from NAND gate 40 is inverted through inverter 42 to output a low signal. The low signal output from inverter 42 is input to the 2.5 V mode selection terminal of the internal circuit 18. The high signal output from inverter 28 and the low signal output from inverter 42 are input to NOR gate 44. NOR gate 44 NORs its two input signals and outputs a low signal, which is input to the 3.3 V mode selection terminal of the internal circuit 18.
In addition, the low signal output from inverter 38 and the low signal output from inverter 42 are input to NOR gate 46. NOR gate 46 NORs the two input signals and outputs a high signal to the 1.8 V mode selection terminal. Accordingly, the internal circuit 18 has a high signal input to the 1.8V mode selection terminal, and operates in a 1.8 V mode.
In a case where the 3.3 V mode selection pad 10 and the 1.8 V mode selection pad 14 (FIG. 1) both are not bonded to the lead frame, the 2.5 V mode is selected. In this case, the 1.8 V mode selection signal and the 3.3 V mode selection signal are both pulled low. The 3.3 V mode selection signal is inverted through inverters 24, 26, 28 and output as a high signal, which is input to an input terminal of NAND gate 40. The 1.8 V mode selection signal is through inverters 34, 36, 38 and output as a high signal, which is input to the other input terminal of NAND gate 40. NAND gate 40 NANDs the high signals that are input to its two input terminals, thereby generating a low output signal. The low signal output from NAND gate 40 is inverted through inverter 42 to output a high signal. The high signal output from inverter 42 is input to the 2.5 V mode selection terminal of the internal circuit 18.
The high signal output from the inverter 28 and the high signal output from inverter 42 are input to NOR gate 44. NOR gate 44 NORs its two input signals and outputs a low signal, which is input to the 3.3 V mode selection terminal of the internal circuit 18.
In addition, the high signal output from inverter 38 and the high signal output from inverter 42 are input to NOR gate 46. NOR gate 46 NORs the two input signals and outputs a low signal to the 1.8 V selection terminal. Accordingly, the internal circuit 18 has a high signal input to the 2.5V mode selection terminal, and operates in a 2.5 V mode.
Once the bonding option circuit as described above is bonded and packaged, the circuit operates only at the internal voltage mode that is bonded therein. Thus, the internal circuit cannot be changed to other internal voltage modes, nor can it be tested at the other internal voltage modes.